(1) Field of the Invention
The present invention relates to a fabrication process used to create metal oxide semiconductor field effect transistor, (MOSFET), devices, and more specifically to a fabrication sequence used to integrate devices, with different gate insulator thicknesses, and a capacitor structure, on a semiconductor chip.
(2) Description of Prior Art
The quest for increased device performance, as well as the goal of decreasing manufacturing costs, have directed the semiconductor industry to micro-miniaturization, or the creation of semiconductor devices, with sub-micron features. Micro-miniaturization has been mainly achieved via advances in specific semiconductor fabrication disciplines, such as photolithography and dry etching. The use of more advanced exposure tools, as well as the development of more sensitive photoresist materials, have enabled sub-micron features to be routinely obtained in photoresist layers. In addition the development of advanced dry etching tools and processes have allowed these sub-micron features, in masking photoresist layers, to be successfully transferred to underlying materials, used in the fabrication of advanced semiconductor devices.
The use of sub-micron features, such as sub-micron channel lengths for MOSFET devices, have led to the use of thin gate insulator layers, which in turn has allowed supply voltages in the range of about 3.3 V, to be used. The use of lower voltages reduce the reliability risk of hot electron injection, sometimes encountered using power 5.0 V, I/Os. However specific peripheral chip functions may still be comprised of longer channel lengths and thicker gate insulator layers, therefore needing the 5.0 supply voltage. Therefore fabrication processes, allowing MOSFET devices to be created, with different gate insulator layer thicknesses, is needed. In addition specific analog functions need capacitor structures that facilitate the operation of the analog integrated circuit. Therefore it would be beneficial to develop a fabrication process that allows the integration of a capacitor structure, exhibiting good voltage and temperature capacitance coefficients, with MOSFET devices, having different gate insulator layer thicknesses.
This invention will describe a fabrication process featuring the creation of MOSFET devices using dual gate insulator layer thicknesses, without covering either silicon surface with photoresist layers, prior to either gate insulator growth. In addition the capacitor structure is formed using a mixed mode procedure, using the polysilicon layers, also used for both gate structures of two MOSFET devices, as capacitor plates, while using one of the gate insulator layers, for the capacitor dielectric layer. Prior art, such as Lin, in U.S. Pat. No. 5,502,009, describes the creation of gate oxide layers, of different thicknesses using a silicon nitride layer to protect a first region, from the formation of a gate insulator layer on a second region. In contrast, this invention features a polysilicon layer, masking a first gate insulator layer, from an oxidation procedure used to create a second gate insulator layer, in a second region. In addition the masking polysilicon layer is subsequently patterned to form a polysilicon gate structure for a first MOSFET device, and to form a plate, for a subsequent capacitor structure.